A semiconductor device is required to be driven with low voltage, low power dissipation and a high operating frequency. In particular, the semiconductor device, used for e.g. a mobile device, is required to be driven not only with low power dissipation but with a high operating speed in keeping up with increase in the amount of data to be processed.
However, these requirements are in a trade-off relationship to one another. That is, in case it is attempted to decrease the power dissipation, the operating speed is lowered, whereas, in case it is attempted to improve the operating speed, the power dissipation is increased.
FIG. 7 is a diagram illustrating a typical example of a conventional serial to parallel conversion circuit. Referring to FIG. 7, this conventional circuit is described. In this figure, plural (herein n) flip-flops FF1 to FFn, connected in cascade, are D flip-flops (edge-triggered flip-flops), each having a resetting function, and compose a shift register, whilst plural (herein n) latches LT1 to LTn are D latches (level-sensitive latches), forming a data register. These n latches LT1 to LTn are supplied at clock input terminals C thereof with data sampling signals S1 to Sn, output from data output terminals Q of the flip-flops FF1 to FFn, forming the shift register, respectively, while receiving data DOn, output from a control block CONT, at data input terminals D thereof, and sampling the so received data, to output the so sampled data in parallel at the data output terminals Q as outputs O1 to On. Meanwhile, the data signal DOn, output from the control block CONT, is of a k-bit width, where k is a positive integer not less than 1. In case k is not less than 2, the latch LT1, supplied with k-bit data in parallel, is formed by a set of k latches. The control block CONT is supplied with a data transfer start pulse STP, a data input Dn (k bits), a transfer clock signal CLK and a reset signal RES to output a data transfer start pulse STPO, a shift clock CLKO and a data output DnO in synchronism with the shift clock CLK.
When supplied with the data transfer start pulse STP, the shift register (FF1 to FFn) is activated by the shift clock signal CLKO to generate respective data sampling signals S1 to Sn. The data signal Dn, entered in synchronization with the data transfer start pulse STP, is sampled and output by the data registers LT1 to LTn, by the respective data sampling signals S1 to Sn, generated by the shift register.
FIG. 8 illustrates the operating timing of the circuit shown in FIG. 7. Referring to FIG. 8, the operation of the circuit shown in FIG. 7 is explained. The D flip-flop FF1, forming the shift register, samples a high level output of the data transfer start pulse STPO with the falling edge of the clock CLKO to output a high level data sampling signal S1, while sampling a low level output thereof with the falling edge of the clock signal CLKO to output the low level data sampling signal S1. As from this time, the data transfer start pulse STPO is transferred in the second and the following stages of the shift register, that is, the flip-flops FF2 to FFn.
In the D latch LT1, during the high level period of the data sampling signal S1, the data input to a data input terminal D is passed to the data output terminal, as it is. When the data sampling signal S1 undertakes a transition from a high level to a low level, the D latch LT1 holds and outputs the data directly before the transition. By the above processing, serial data D11 to D1n are output from latch outputs O1 to On in parallel.
Referring to FIG. 8, the maximum operating frequency of the circuit shown in FIG. 7 is the frequency of the shift clock signal CLKO fed to the shift register (FF1 to FFn) which generates data sampling signals S1 to Sn, and the frequency of the clock line for propagating the shift clock signal is the transfer frequency (transfer rate) of the data signal Dn on a data line. It is noted that, in case the transfer of the data signal on the data line is to be effected using both the rising and falling edges of the transfer clock (double data rate), the frequency of the shift clock signal CLKO is twice the transfer clock signal on the data line.
If a signal line in need of an operating speed in excess of the targeted operation is used in a circuit intrinsically aimed to transfer the data, the result is the lowered maximum operating frequency of the circuit and the increased power dissipation.
In particular, in a serial to parallel conversion circuit, targeted at data transfer, the length of the signal line and the load of the line are increased. In such case, a signal line having a high operating speed, such as a clock line of FIG. 7, is deterrent to decreasing the driving voltage, operating frequency and the power dissipation.
As a shift register of low power dissipation, there is known a configuration in which storage circuits are connected in series, the gate circuits in odd-numbered storage circuits are turned on with the high level of the clock signals, the gate circuits in the even-numbered storage circuits are turned on with the low level of the clock signals, and the data entered are latched in case the gate circuits are turned off, and the data are subsequently output, with the operation of the shift register taking place every one-half period of the clock period, thereby enabling the frequency of the clock signals to be halved (for example, see Patent Document 1).
There has also been known a configuration in which the operating frequency of the shift register is designed to be one-half the input frequency, and in which the shift register is operated at the so halved frequency to reduce the power dissipation and the noise (for example, see Patent Document 2).
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2003-115194A (pages 4 to 5, FIG. 1).
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-10-232656 (pages 3 and 4 and FIG. 1).